Following the advancement in scientific technologies, the process technique for flash memory has also moved into the nano era. To enable increased device operating speed, high integration density of a device, reduced the device operating voltage, etc., it has become an inevitable trend to minimize the gate channel length and the oxide layer thickness of the semiconductor device. The measure of gate line width has been reduced from the past micrometer (10−6 meter) to the current nanometer (10−9 meter). However, the device size reduction also brings many problems, such as stress-induced leakage current (SILC) and worsened short channel effect due to reduced gate line width. To avoid the device from being adversely affected by the short channel effect, the oxide layer thereof must have a thickness as small as possible. However, when the oxide layer has a thickness of 8 nm or below, the physical limit of material thereof would become a barrier in the manufacturing process of the device. By the SILC, it means an increased leakage current at the gate of a device after a constant voltage stress or a constant current stress is applied to the device. When the oxide layer is reduced in its thickness, the SILC becomes a very important issue. Increase of the SILC would lead to loss of electrons retained in the floating gate and accordingly, largely lowered data retention ability and increased power consumption of the metal-oxide-semiconductor (MOS) device. Further, the gate disturb and drain disturb in memory cells also largely restrict the thickness of the oxide layer during the course of size reduction of the device. Therefore, when the device size has reached its physical limit, it becomes a very urgent need to find a way other than the device size reduction to overcome the shortcomings brought by the reduced device size.
To improve the current performance in the device, there are many ways for increasing the carrier mobility. One of these ways is the already known strained Si channel approach, in which stressed Si channel is formed. The stress is helpful in increasing the mobility of electrons or holes, so that the characteristics of MOS device may be improved via the stressed channel. The application of stress is also beneficiary to the reduction of the gate disturb and drain disturb in memory cells. That is, a relatively higher drain current may be obtained while a relatively lower drain voltage is used. Therefore, only a lowered drain voltage is needed to achieve the initially required drain current to thereby enable reduced the gate and drain disturb.
The increase of stress may be achieved by the formation of a stressed layer on the MOS device. A contact etch stop layer (CESL) may serve as the stressed layer. In depositing the stressed layer, an in-planar stress is yielded to result in energy band separation. Please refer to FIG. 7 that describes the relation between the stress direction and the energy band in a MOS semiconductor. That is, there is a rising energy band at the fourfold degenerate (Δ4) energy valley corresponding to the kx and ky directions in the space k, and a lowering energy band at the twofold degenerate (Δ2) energy valley corresponding to the kz direction in the space k. Therefore, most of the electrons are distributed in the Δ2 energy valley having lower energy band (i.e., having lower effective mass). In addition, a strain-induced band splitting, in the one hand, reduces the inter-valley scattering rate (or optical phonon scattering rate), and, on the other hand, reduces the effective density of state in the conduction band to thereby reduce the intra-valley scattering rate (or acoustic phonon scattering rate). Therefore, the lowered effective mass and scattering rate is helpful in improving the electron mobility. Similarly, the separated energy-degenerate light-hole band and heavy-hole band in the valence band as well as the lowered inter-band and the intra-band scattering rate are also enable the hole mobility improved. However, an overly thick stressed layer would lead to difficulty in subsequent gap filling, while an overly thin stressed layer would lead to limited the stress effect.
It is therefore very important to enhance the device characteristics through improvement in the stressed layer and other arrangements related thereto without complex design of the device.